This invention relates to EPROM and semiconductor devices and the like and in particular to EPROM devices having both N-channel and P-channel peripheral devices.
Erasable programmable read only memories are well known in the semiconductor art. EPROM circuits include a matrix of EPROM devices, each of which stores a bit of information, and a plurality of peripheral transistor devices. Peripheral transistors are required for such functions as row decode and column decode of the EPROM matrix, latches and drivers.
In addition to having a control gate similar to the control gate of the peripheral devices, EPROM devices have a floating gate positioned below the control gate. It is this floating gate which allows the EPROM device to store charge, thereby programming the EPROM device. Conversely, when the EPROM device is unprogrammed, the floating gate is uncharged.
The architecture required places constraints on the size of the EPROM device. Since the floating gate must rest directly below the control gate, both gates must be large enough to allow their proper alignment. Self-alignment of both the control gate and the floating gate allows a reduction in the size of the EPROM device.
Most conventional commercial EPROM integrated circuits are NMOS wherein both the EPROM and all the peripherals are N-channel devices. The inability in practice to use P-channel transistors where their use would be beneficial has resulted in the need for a greater number of transistors (all N-channel) to perform a desired function using only N-channel transistors as well as a much larger power consumption. Peripheral circuitry could be reduced in size if both N-channel and P-channel transistors were used in the peripherals. Heretofore, no method has been known for integrating EPROM devices with both N-channel and P-channel transistors, that is capable of producing self-aligned gates in the EPROM devices.
EPROM integrated circuits are known that employ N-channel and P-channel transistors in the control circuits peripheral to the EPROM memory array which itself is usually made of N-channel memory cells. However, little has been disclosed of the integrated process steps contemplated for making such C-MOS EPROM integrated circuits.
A key factor determining quality and reliability of integrated circuits, and particularly of complex integrated circuits such as the memories under consideration here, is the number of photo-masking steps needed to make the part. This is because the minimum practical size and cost of an integrated circuit is generally limited by the resolution and registration limits of state of the art lithography. Thus for a given photo lithography, the accumulation of masking steps should be kept to the barest minimum to render a process practical.
It is therefore an object of this invention to provide a CMOS EPROM integrated circuit wherein both the floating gate and the control gate are self-aligned.
It is a further object of this invention to provide a process for making such an integrated circuit requiring a relatively small number of photo lithographic masking steps.
It is a further object of this invention to provide in such a CMOS EPROM integrated circuit a very high quality insulation between the floating gate and the control gate of each elemental EPROM device.